1. Field
The following description relates to interrupt handling, for example, interrupt handling in a multi-core processor.
2. Description of the Related Art
A critical section exclusively executed for synchronization may exist at multiple locations in an operating system. For example, the term ‘exclusively’ denotes that a central processing unit (CPU) executes a corresponding process regardless of other conditions. Therefore, when an interrupt signal is generated in the critical section, it is not processed or processing thereof is delayed; regardless of importance or urgency.
In an operating system of a computer, a critical section may be implemented as an interrupt-disabled section, a kernel non-preemptible section, or a combination of the two. The interrupt-disabled section is a section in which an interrupt is not processed since an interrupt handler is not executed. The kernel non-preemptible section is a section in which kernel preemption is not possible since a process switch or a context switch does not occur even if the interrupt handler is executed. In addition to the interrupt-disabled section and the kernel non-preemptible section, the time required to process an interrupt signal may also be considered as a critical section in a broad sense. This is because a CPU processing a specified interrupt may not process other interrupts until processing of the specified interrupt is finished.
A critical section, such as the interrupt-disabled section and/or the kernel non-preemptible section, prevents a problem with synchronization, which may result from interrupt handling, in an operating system. Therefore, the critical section exists in an operating system of a computer. However, the critical section causes delay in the execution of an urgent interrupt which wakes up a real-time process that should be processed quickly. Even in a multi-core system, delay in the processing of an urgent interrupt due to the critical section tends to be unavoidable. To prevent delay in the processing of an urgent interrupt, various techniques have been suggested, such as a lock breaking technique, a dual kernel technique, a shielded CPU technique, and a delayed locking technique.